`timescale 1ns / 1ps

module divider_1khz(
    input clk_i,                // 100MHz input
    output reg clk_o = 'b0      // 1kHz output
    );
    parameter cnt_max = 100000;     // 100M/1k = 100000
    parameter cnt_half = cnt_max/2;

    reg [19:0] cnt = 'b0;

    always @(posedge clk_i) begin
        clk_o <= (cnt>cnt_half) ? 1'b1 : 1'b0;
        cnt <= (cnt>=cnt_max) ? 'b1 : cnt+1;
    end
endmodule
